Furthermore, the width of a register must be specified by the user either explicitly or from the bitwidth of the reset value. See Figure 3 for successively more complicated examples. a = UInt(1)b = a & UInt(2)b | UInt(3) Figure 3: Chisel Op/Lit graphs constructed with algebraic expressions showing the insertion of type nodes. After all connections are made and the circuit is being elaborated, Chisel warns users if ports have other than exactly one connection to them. This means you can implement the functionality of the BlackBox using the io so that you can verify your design. Because they do not have cycles, legal combinational circuits can always be constructed in a feed-forward manner, by adding new nodes whose inputs are derived from nodes that have already been defined. Because Scala evaluates program statements sequentially, we have allowed data nodes to serve as a wire providing a declaration of a node that can be used immediately, but whose input will be set later.
During simulation, if an assertion’s argument is false on a rising clock edge, an error is printed and simulation terminates. Use the function setName() to set the names for nodes or submodules. For example, the output of a Data node can be referenced immediately, but its input can be set later.
Connections are only made if one of the ports is non-null, allowing users to repeatedly bulk-connect partially filled interfaces. Chisel type nodes are erased before the hardware design is translated into C++ or Verilog. Black boxes allow users to define interfaces to circuits defined outside of Chisel. The bit-width inference process continues until no bit width changes. User code in Chisel generate this graph of nodes, which is then passed to the Chisel backends to be translated into Verilog or C++ code. The Chisel type system is maintained separately from the underlying Scala type system, and so type nodes are interspersed between raw nodes to allow Chisel to check and respond to Chisel types.